The present invention relates generally to the field of statistical static timing analysis, and more particularly to performing multi-sided variations that result in timing quantities, in which the timing quantities enable projection to a specified process/voltage point within a parameter space.
An integrated circuit (also known as a microcircuit, a microchip, a silicon chip, or a chip) is a miniaturized electronic circuit consisting of mainly semiconductor devices and passive components, manufactured in a surface of a thin substrate of semiconductor material. The integrated circuit is constructed from small electronic circuits called logic gates (i.e., an idealized or physical device implementing a Boolean function that performs a logical operation on one or more logical inputs) that produces a single logical output resulting in an electrical flow or voltage, which can control more logic gates. Operation of the integrated circuit is characterized by a clock frequency (e.g., clock signal). The clock signal oscillates between a high and a low state to coordinate actions of integrated circuits. The logic gates can control the clock signal to effectively enable or disable a portion of the integrated circuit. To gauge the ability of the integrated circuit to operate at a specified speed, measurements of the delays are taken throughout the design process.
Delay calculation, calculates the gate delay (i.e., a length of time between when the input to a logic gate becomes stable and valid to change to the time that the output of that logic gate is stable and valid to change) of a single logic gate (i.e.,) and the delay created by the attached wires. Calculation of the gate delay may be provided by circuit simulators, two dimensional tables (e.g., logic synthesis), placement and routing (i.e., tables take an output load and input slope, and generate a circuit delay and output slope), and K factor models (i.e., approximates the delay as a constant plus k times the load capacitance). Calculation of the wire delay may be provided by a lumped C (i.e., entire wire capacitance is applied to the gate output, and the delay through the wire itself is ignored), an Elmore delay (i.e., delay of each wire segment is an electrical resistance (R) of that segment times the electrical capacitance (downstream C), moment matching (i.e., matches multiple moments in the time domain, or finds a good rational approximation in the frequency domain), and circuit simulators.
Static timing analysis (STA) is an input-independent method of analyzing a frequency or a clock rate (e.g., validating the timing performance) for an integrated circuit by simulating the delays of entire paths of an integrated circuit without requiring a simulation of the full integrated circuit. STA breaks down the design of the integrated circuit into a set of timing paths, calculates the signal propagation delay along each path (i.e., time required for a digital signal to travel from the input of a logic gate to the output), and checks for violations of timing constraints. Two kinds of violations (e.g., timing errors) are possible: a setup time violation and a hold time violation. A setup time violation is based on a setup constraint that specifies an amount of time that is necessary for data to be available (e.g., stable) at the input of a sequential device before the clock edge that the input signal needs to guarantee the input signal is properly accepted on the clock edge that captures the data in the device. The hold time violation is based on a hold constraint that specifies how much time is necessary for data to be stable at the input of a sequential device after receiving the clock edge (i.e., the hold constraint enforces a minimum delay on the data path relative to the clock path).
Statistical static timing analysis (SSTA) is an alternative to STA. SSTA replaces fixed or normal deterministic timing of gates and interconnects with probability distributions (e.g., a range of probabilities), thereby returning a distribution of possible circuit outcomes rather than a single outcome. SSTA employs a sensitivity based approach to model the effect of variations on timing by determining how a change in a particular device or interconnect parameter (e.g., oxide, wire thickness, etc.) affects a desired property (e.g., slew, capacitance, etc.). The sensitivity to the parameter in conjunction with the probability distribution (i.e., mean and standard deviation) provides a statistical model describing the probability that a parameter will have a certain effect on a device or interconnect property. SSTA uses sensitivities to identify correlations among delays, and utilizes the correlations when computing how to add statistical distributions of delays (i.e., model the effect on timing). The SSTA maps the standard deviations with respect to the devices and interconnect parameters to obtain an overall standard deviation of the path delay. SSTA includes a path-based method and a block based method. The path based method sums gate and wire delays on specific paths. The block-based method generates the arrival times and required times for each node, working both forward and backward from the clocked elements.